1. Field of the Invention
The present invention relates generally to a searcher used to synchronize a mobile station in an IS-95/cdma2000 system and a method thereof, and in particular, to a searcher which can reduce a dummy time using an improved method of moving a PN (Pseudorandom Noise) sequence offset.
2. Description of the Related Art
In an IS-95/cdma2000 system, a base station transmits a pilot signal on a forward link and a mobile station synchronizes its timing to the base station by acquisition of the pilot signal. For acquisition and tracking of the pilot signal, the mobile station uses a searcher. The searcher detects the strength and position of the pilot signal by calculating the energy of a received signal while changing a PN sequence offset by the same short PN(Pseudo-random Noise) code generator as used in the base station. Here, each PN sequence offset used for pilot acquisition is called a PN hypothesis.
FIG. 1 is a schematic block diagram of a prior art searcher. Referring to FIG. 1, the searcher is comprised of despreaders 101 and 102 for despreading I and Q data with a PN sequence, respectively; correlators 103 and 104 for accumulating the despread data respectively; squarers 105 and 106 for calculating accumulated energy values; an adder 107 for adding the outputs of the squarers 105 and 106; a non-coherent accumulator 108 for non-coherently accumulating the sum received from the adder 107; a comparator 109 for comparing the energy of the non-coherent accumulation value with a threshold, the comparator 109 generating a pilot detection signal if the energy exceeds the threshold, and generates a PN delay signal if the energy is equal to or smaller than the threshold, a PN clock generator 111 for generating a PN delay clock by the PN delay signal of the comparator; and a PN sequence generator 110 for delaying a PN sequence as much as the delayed clock and outputting that to the despreaders 101 and 102 when the delayed clock is inputted from the PN clock generator 111.
A PN sequence is generated using characteristic polynomials like Eq. 1 in the IS-95/cdma2000 system. The PN sequence is of period 215 chips (26.66 ms) and produces 215 (32,768) PN hypotheses.PI(x)=x15+x14+x9+x8+x7+x5+1PQ(x)=x15+x14+x11+x10+x6+x5+x4+x3+1  (1)
The prior art searcher as shown by FIG. 1 changes a PN hypothesis by delaying and applying the PN sequence with respect to a received signal. FIG. 2 is a detailed construction of the PN clock generator 111 and the PN sequence generator 110 of FIG. 1.
The comparator 109 of FIG. 1 generates the PN delay signal to shift to a next PN hypothesis if an energy value related with the present PN hypothesis does not exceed the threshold and feeds the PN delay signal to the PN clock masking block 202 to thereby preventing block a PN clock signal from being fed to the PN sequence generator 203.
FIG. 3 is a signal diagram illustrating a PN hypothesis moving method in a one-multiple speed searcher. Referring to FIG. 3, if the present PN hypothesis is an Nth PN hypothesis, the memory state of a PN sequence generator is delayed by one chip to shift to an (N+1)th PN hypothesis.
FIG. 4 is a signal diagram illustrating a PN hypothesis moving method in an M-multiple speed searcher. Referring to FIG. 4, the M-multiple speed searcher checks M PN hypotheses at the same time for one correlation length, thereby searching for a pilot signal M times faster than the one-multiple searcher. If the present PN hypothesis is an Nth PN hypothesis, the M-multiple speed searcher despreads the M PN hypotheses by delaying a corresponding PN sequence using an M-tap shift register. Then, the M-multiple speed searcher calculates energy values related to the M PN hypotheses by time-multiplexing the despreading results using a clock signal faster than a chip rate. Since the M-multiple speed searcher applies from Nth PN hypothesis to (N+M−1)th PN hypothesis, if the correlations of the M PN hypotheses are calculated and an energy value related with the present PN hypothesis does not exceed the threshold, the M-multiple speed searcher should shift to (N+M)th PN hypothesis to detect a next PN hypothesis. That is, As shown in FIG. 4, the M-multiple speed searcher holds the memory state of the PN sequence generator by M chips to use the M PN hypotheses after applying the M PN hypotheses. As a result, the PN sequence is delayed from the received data by M chips.
In this method, a 16-multiple speed searcher must wait for 16 chips and a 32-multiple speed searcher must wait for 32 chips in order to shift to a next PN hypothesis. As compared to a one-multiple speed searcher, the M-multiple speed searcher consumes an M-chip dummy time to shift to a next PN hypothesis.
As described above, the conventional searchers delay PN sequences to shift to next PN hypotheses. Therefore, a dummy time required for changing a PN hypothesis increases in proportion to a search speed.